The present invention relates in general to complementary metal-oxide-silicon (CMOS) filters, and in particular to a circuit technique to implement programmable zeros in high speed CMOS filters.
The major technical challenge to implement a filter with equalization function using CMOS technology is the considerably lower transconductance for MOS transistors compared to their bipolar counterparts. The circuit techniques used in BiCMOS process are not applicable to the CMOS process. To implement two real zeros using CMOS technology, the general approach is to sum or subtract the band-pass output from the low-pass output of a preceding biquad stage.
FIG. 1 shows a block diagram of a 7-pole 2-zero filter/equalizer. It consists of three biquads 100, 102, and 104, and a monoquad 106. Each biquad generates a low-pass output v.sub.o, and a band-pass output v.sub.b. The last block 106 has two identical monoquads connected in parallel to the low-pass output and the band-pass output of the third biquad to provide a real pole. Each of the second and the third biquads generates a real zero in addition to two complex poles to provide both magnitude and group delay equalization. The magnitude equalization is realized by moving the real zeros from infinite to finite values on the real axes. The group delay equalization is implemented by programming the two real zeros non-symmetrically about the origin of S-plane.
FIG. 2 shows a block diagram of a typical transconductor-based biquad to implement the second biquad 102. The biquad 102 includes two integration stages 200 and 202. The first integration stage 200 includes a feedback transconductance element -g.sub.m, a band-pass input-controlled transconductance element -k.sub.1 g.sub.m, and a low-pass input-controlled transconductance element g.sub.m. Capacitors C1 and C2 are the integration capacitors, and damping transconductor g.sub.d provides the required damping effect. The first integration stage 200 receives the low-pass output v.sub.o1 and the band-pass output v.sub.b1 from the previous biquad (100). A zero is realized by summing the band-pass output and the low-pass output of the first biquad 100 in the form of current at node v.sub.b2. Compared to the standard 2-pole biquad, one extra transconductor is needed to implement the second biquad 102. The position of the zero which corresponds to the magnitude and group delay equalization can be changed by varying the coefficient k.sub.1. To achieve a maximum magnitude equalization of, for example, 6.5 dB at the corner frequency of the filter, k.sub.1 would have to equal approximately 2.137, a relatively large multiplier factor.
Designing a circuit that implements such a transconductor in the biquad poses several challenges. Integrated circuit implementations of filters typically use the same type of transconductors for all of the transconductance elements including the zero-implementing (equalization) transconductor. This approach results in a large parasitic capacitance at the band-pass output node as compared to the low-pass output node. To alleviate this problem, a separate summing stage is often used to implement the zero. However, the summing stage in this approach introduces an extra pole in the signal path which causes phase lag error. Moreover, power consumption is usually increased significantly because the transconductor required to implement the equalization function is much larger than the other transconductors of the biquad. That is, to obtain a large value for -k.sub.1 g.sub.m, larger transistor sizes or larger currents are required. This also adds to the circuit size and thus cost of manufacture.
There is therefore a need for a circuit technique that efficiently implements programmable zeros in CMOS filters with reduced parasitics, power consumption and circuit size.